ADT7463
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36
Table 46. VOLTAGE READING REGISTERS (POWERON DEFAULT = 0X00) (Note 1)
Register Address
R/W
Description
0x20
Readonly
2.5 V Reading (8 MSBs of Reading)
0x21
Readonly
V
CCP
Reading: Holds Processor Core Voltage Measurement (8 MSBs of Reading)
0x22
Readonly
V
CC
Reading: Measures V
CC
through the V
CC
Pin (8 MSBs of Reading)
0x23
Readonly
5 V Reading (8 MSBs of Reading)
0x24
Readonly
12 V Reading (8 MSBs of Reading)
1. If the extended resolution bits of these readings are also being read, the extended resolution registers (Reg. 0x76, 0x77) should be read first.
Once the extended resolution registers get read, the associated MSB reading registers get frozen until read. Both the extended resolution
registers and the MSB registers get frozen.
Table 47. TEMPERATURE READING REGISTERS (POWERON DEFAULT = 0X80) (Note 1)
Register Address
R/W
Description
0x25
Readonly
Remote 1 Temperature Reading (8 MSBs of reading) (Note 2)
0x26
Readonly
Local Temperature Reading (8 MSBs of Reading)
0x27
Readonly
Remote 2 Temperature Reading (8 MSBs of reading) (Note 2)
1. These voltage readings are in twos complement format.
2. Note that a reading of 0x80 in a temperature reading register indicates a diode fault (open or short) on that channel. If the extended resolution
bits of these readings are also being read, the extended resolution registers (Reg. 0x76, 0x77) should be read first. Once the extended
resolution registers are read, the associated MSB reading registers are frozen until read. Both the extended resolution registers and the MSB
registers are frozen.
Table 48. FAN TACHOMETER READING REGISTERS (POWERON DEFAULT = 0X00) (Note 1)
Register Address
R/W
Description
0x28
Readonly
TACH1 Low Byte
0x29
Readonly
TACH1 High Byte
0x2A
Readonly
TACH2 Low Byte
0x2B
Readonly
TACH2 High Byte
0x2C
Readonly
TACH3 Low Byte
0x2D
Readonly
TACH3 High Byte
0x2E
Readonly
TACH4 Low Byte
0x2F
Readonly
TACH4 High Byte
1. These registers count the number of 11.11 ms periods (based on an internal 90 kHz clock) that occur between a number of consecutive fan
TACH pulses (default = 2). The number of TACH pulses used to count can be changed using the fan pulses per revolution register
(Reg. 0x7B). This allows the fan speed to be accurately measured. Since a valid fan tachometer reading requires that two bytes are read,
the low byte MUST be read first. Both the low and high bytes are then frozen until read. At poweron, these registers contain 0x0000 until
such time as the first valid fan TACH measurement is read in to these registers. This prevents false interrupts from occurring while the fans
are spinning up.
A count of 0xFFFF indicates that a fan is:
" Stalled or blocked (object jamming the fan).
" Failed (internal circuitry destroyed).
" Not populated. (The ADT7463 expects to see a fan connected to each TACH. If a fan is not connected to that TACH, its TACH minimum
high and low byte should be set to 0xFFFF.)
" Alternate function, for example, TACH4 reconfigured as a THERM
pin.
" 2wire Instead of 3wire Fan
Table 49. CURRENT PWM DUTY CYCLE REGISTERS (POWERON DEFAULT = 0XFF) (Note 1)
Register Address
R/W
Description
0x30
R/W
PWM1 Current Duty Cycle (0% to 100% Duty Cycle = 0x00 to 0xFF).
0x31
R/W
PWM2 Current Duty Cycle (0% to 100% Duty Cycle = 0x00 to 0xFF).
0x32
R/W
PWM3 Current Duty Cycle (0% to 100% Duty Cycle = 0x00 to 0xFF).
1. These registers reflect the PWM duty cycle driving each fan at any given time. When in automatic fan speed control mode, the ADT7463
reports the PWM duty cycles back through these registers. The PWM duty cycle values vary according to temperature in automatic fan speed
control mode. During fan startup, these registers report back 0x00. In software mode, the PWM duty cycle outputs can be set to any duty
cycle value by writing to these registers.
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